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IEEE Standard for Ethernet - Amendment 3: Physical Layer Specifications and Management Parameters for 40 Gb/s and 100 Gb/s Operation over Fiber Optic Cables, 2015
- IEEE Std 802.3bm-2015 Front Cover
- Title page
- Important Notices and Disclaimers Concerning IEEE Standards Documents
- Participants
- Introduction
- Contents
- 1. Introduction [Go to Page]
- 1.1 Overview [Go to Page]
- 1.1.3 Architectural perspectives [Go to Page]
- 1.1.3.2 Compatibility interfaces
- 1.3 Normative references
- 1.4 Definitions
- 1.5 Abbreviations
- 22. Reconciliation Sublayer (RS) and Media Independent Interface (MII) [Go to Page]
- 22.2 Functional specifications [Go to Page]
- 22.2.4 Management functions [Go to Page]
- 22.2.4.3 Extended capability registers
- 30. Management [Go to Page]
- 30.5 Layer management for medium attachment units (MAUs) [Go to Page]
- 30.5.1 MAU managed object class [Go to Page]
- 30.5.1.1 MAU attributes
- 45. Management Data Input/Output (MDIO) Interface [Go to Page]
- 45.2 MDIO Interface Registers [Go to Page]
- 45.2.1 PMA/PMD registers [Go to Page]
- 45.2.1.3 PMA/PMD device identifier (Registers 1.2 and 1.3)
- 45.2.1.6 PMA/PMD control 2 register (Register 1.7)
- 45.2.1.7 PMA/PMD status 2 register (Register 1.8)
- 45.2.1.8 PMD transmit disable register (Register 1.9)
- 45.2.1.12 40G/100G PMA/PMD extended ability register (Register 1.13)
- 45.2.1.92aa CAUI-4 chip-to-module recommended CTLE register (Register 1.179)
- 45.2.1.92ab CAUI-4 chip-to-chip transmitter equalization, receive direction, lane 0 register (Register 1.180)
- 45.2.1.92ac CAUI-4 chip-to-chip transmitter equalization, receive direction, lane 1 through lane 3 registers (Registers 1.181, 1.182, 1.183)
- 45.2.1.92ad CAUI-4 chip-to-chip transmitter equalization, transmit direction, lane 0 register (Register 1.184)
- 45.2.1.92ae CAUI-4 chip-to-chip transmitter equalization, transmit direction, lane 1 through lane 3 registers (Registers 1.185, 1.186, 1.187)
- 45.2.3 PCS registers [Go to Page]
- 45.2.3.46 Lane 0 mapping register (Register 3.400)
- 69. Introduction to Ethernet operation over electrical backplanes [Go to Page]
- 69.1 Overview [Go to Page]
- 69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model
- 69.2 Summary of Backplane Ethernet Sublayers [Go to Page]
- 69.2.3 Physical Layer signaling systems
- 74. Forward Error Correction (FEC) sublayer for BASE-R PHYs [Go to Page]
- 74.4 Inter-sublayer interfaces
- 74.5 FEC service interface
- 78. Energy-Efficient Ethernet (EEE) [Go to Page]
- 78.1 Overview [Go to Page]
- 78.1.1 LPI Signaling
- 78.1.3 Reconciliation sublayer operation [Go to Page]
- 78.1.3.3 PHY LPI operation
- 78.1.4 PHY types optionally supporting EEE
- 78.5 Communication link access latency [Go to Page]
- 78.5.2 40 Gb/s and 100 Gb/s PHY extension using XLAUI or CAUI-n
- 80. Introduction to 40 Gb/s and 100 Gb/s networks [Go to Page]
- 80.1 Overview [Go to Page]
- 80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
- 80.1.4 Nomenclature
- 80.1.5 Physical Layer signaling systems
- 80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers [Go to Page]
- 80.2.3 Forward Error Correction (FEC) sublayers
- 80.2.5 Physical Medium Dependent (PMD) sublayer
- 80.4 Delay constraints
- 80.5 Skew constraints
- 80.7 Protocol implementation conformance statement (PICS) proforma
- 81. Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb/s and 100 Gb/s operation (XLGMII and CGMII) [Go to Page]
- 81.3a LPI Assertion and Detection [Go to Page]
- 81.3a.2 Transmit LPI state diagram [Go to Page]
- 81.3a.2.1 Variables and counters
- 81.3a.4 Considerations for receive system behavior
- 82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R [Go to Page]
- 82.1 Overview [Go to Page]
- 82.1.4 Inter-sublayer interfaces
- 82.2 Physical Coding Sublayer (PCS) [Go to Page]
- 82.2.6 Block distribution
- 83. Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R [Go to Page]
- 83.1 Overview [Go to Page]
- 83.1.1 Scope
- 83.1.4 PMA sublayer positioning
- 83.2 PMA Interfaces
- 83.3 PMA service interface
- 83.4 Service interface below PMA
- 83.5 Functions within the PMA [Go to Page]
- 83.5.1 Per input-lane clock and data recovery
- 83.5.3 Skew and Skew Variation [Go to Page]
- 83.5.3.a Skew generation toward SP0
- 83.5.3.1 Skew generation toward SP1
- 83.5.3.2 Skew tolerance at SP1
- 83.5.3.3 Skew generation toward SP2
- 83.5.3.5 Skew generation at SP6
- 83.5.3.6 Skew tolerance at SP6
- 83.5.3.7 Skew generation towards SP7
- 83.5.6 Signal drivers
- 83.5.10 PMA test patterns (optional)
- 83.5.11 Energy Efficient Ethernet [Go to Page]
- 83.5.11.3 Additional transmit functions in the Tx direction
- 83.5.11.4 Additional receive functions in the Tx direction
- 83.5.11.5 Additional transmit functions in the Rx direction
- 83.5.11.6 Additional receive functions in the Rx direction
- 83.7 Protocol implementation conformance statement (PICS) proforma for Clause 83, Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R [Go to Page]
- 83.7.3 Major capabilities/options
- 83.7.5 Test patterns
- 83.7.7 EEE deep sleep with XLAUI/CAUI-n
- 85. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10 [Go to Page]
- 85.1 Overview
- 85.3 PCS requirements for Auto-Negotiation (AN) service interface
- 85.13 Protocol implementation conformance statement (PICS) proforma for Clause 85, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10 [Go to Page]
- 85.13.3 Major capabilities/options
- 86. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10 [Go to Page]
- 86.1 Overview
- 86.8 Definitions of optical and dual-use parameters and measurement methods [Go to Page]
- 86.8.4 Optical parameter definitions [Go to Page]
- 86.8.4.7 Stressed receiver sensitivity
- 86.10 Optical channel [Go to Page]
- 86.10.1 Fiber optic cabling model
- 87. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–LR4 and 40GBASE–ER4 [Go to Page]
- 87.1 Overview
- 87.2 Physical Medium Dependent (PMD) service interface
- 87.3 Delay and Skew [Go to Page]
- 87.3.1 Delay constraints
- 87.5 PMD functional specifications [Go to Page]
- 87.5.1 PMD block diagram
- 87.6 Wavelength-division-multiplexed lane assignments
- 87.7 PMD to MDI optical specifications for 40GBASE–LR4 and 40GBASE–ER4 [Go to Page]
- 87.7.1 40GBASE–LR4 and 40GBASE–ER4 transmitter optical specifications
- 87.7.2 40GBASE–LR4 and 40GBASE–ER4 receive optical specifications
- 87.7.3 40GBASE–LR4 and 40GBASE–ER4 illustrative link power budgets
- 87.8 Definition of optical parameters and measurement methods [Go to Page]
- 87.8.1 Test patterns for optical parameters
- 87.8.4 Average optical power
- 87.8.6 Transmitter and dispersion penalty [Go to Page]
- 87.8.6.2 Channel requirements
- 87.8.7 Extinction ratio
- 87.8.11 Stressed receiver sensitivity [Go to Page]
- 87.8.11.5 Stressed receiver conformance test procedure for WDM conformance testing
- 87.9 Safety, installation, environment, and labeling [Go to Page]
- 87.9.2 Laser safety
- 87.9.4 Environment [Go to Page]
- 87.9.4.1 Electromagnetic emission
- 87.10 Fiber optic cabling model
- 87.11 Characteristics of the fiber optic cabling (channel) [Go to Page]
- 87.11.1 Optical fiber cable
- 87.11.3 Medium Dependent Interface (MDI) requirements
- 87.12 Requirements for interoperation between 40GBASE-LR4 and 40GBASE-ER4
- 87.13 Protocol implementation conformance statement (PICS) proforma for Clause 87, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4 and 40GBASE-ER4 [Go to Page]
- 87.13.1 Introduction
- 87.13.2 Identification [Go to Page]
- 87.13.2.2 Protocol summary
- 87.13.3 Major capabilities/options
- 87.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4 and 40GBASE-ER4 [Go to Page]
- 87.13.4.3 PMD to MDI optical specifications for 40GBASE-LR4
- 87.13.4.3a PMD to MDI optical specifications for 40GBASE-ER4
- 88. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4 [Go to Page]
- 88.1 Overview
- 89. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-FR [Go to Page]
- 89.1 Overview
- 91. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs [Go to Page]
- 91.2 FEC service interface
- 91.3 PMA compatibility
- 91.5 Functions within the RS-FEC sublayer [Go to Page]
- 91.5.2 Transmit function [Go to Page]
- 91.5.2.7 Reed-Solomon encoder
- 91.5.3 Receive function [Go to Page]
- 91.5.3.3 Reed-Solomon decoder
- 91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs [Go to Page]
- 91.7.3 Major capabilities/options
- 91.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs [Go to Page]
- 91.7.4.1 Transmit function
- 91.7.4.2 Receive function
- 92. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR4 [Go to Page]
- 92.1 Overview
- 92.3 PCS requirements for Auto-Negotiation (AN) service interface
- 92.14 Protocol implementation conformance statement (PICS) proforma for Clause 92, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR4 [Go to Page]
- 92.14.3 Major capabilities/options
- 93. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR4 [Go to Page]
- 93.1 Overview
- 93.3 PCS requirements for Auto-Negotiation (AN) service interface
- 93.11 Protocol implementation conformance statement (PICS) proforma for Clause 93, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR4 [Go to Page]
- 93.11.3 Major capabilities/options
- 94. Physical Medium Attachment (PMA) sublayer, Physical Medium Dependent (PMD) sublayer, and baseband medium, type 100GBASE-KP4 [Go to Page]
- 94.1 Overview
- 94.3 Physical Medium Dependent (PMD) Sublayer [Go to Page]
- 94.3.2 PCS requirements for Auto-Negotiation (AN) service interface
- 94.6 Protocol implementation conformance statement (PICS) proforma for Clause 94, Physical Medium Attachment (PMA) and Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KP4 [Go to Page]
- 94.6.3 Major capabilities/options
- 95. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-SR4 [Go to Page]
- 95.1 Overview [Go to Page]
- 95.1.1 Bit error ratio
- 95.2 Physical Medium Dependent (PMD) service interface
- 95.3 Delay and Skew [Go to Page]
- 95.3.1 Delay constraints
- 95.3.2 Skew constraints
- 95.4 PMD MDIO function mapping
- 95.5 PMD functional specifications [Go to Page]
- 95.5.1 PMD block diagram
- 95.5.2 PMD transmit function
- 95.5.3 PMD receive function
- 95.5.4 PMD global signal detect function
- 95.5.5 PMD lane-by-lane signal detect function
- 95.5.6 PMD reset function
- 95.5.7 PMD global transmit disable function (optional)
- 95.5.8 PMD lane-by-lane transmit disable function (optional)
- 95.5.9 PMD fault function (optional)
- 95.5.10 PMD transmit fault function (optional)
- 95.5.11 PMD receive fault function (optional)
- 95.6 Lane assignments
- 95.7 PMD to MDI optical specifications for 100GBASE-SR4 [Go to Page]
- 95.7.1 100GBASE-SR4 transmitter optical specifications
- 95.7.2 100GBASE-SR4 receive optical specifications
- 95.7.3 100GBASE-SR4 illustrative link power budget
- 95.8 Definition of optical parameters and measurement methods [Go to Page]
- 95.8.1 Test patterns for optical parameters [Go to Page]
- 95.8.1.1 Multi-lane testing considerations
- 95.8.2 Center wavelength and spectral width
- 95.8.3 Average optical power
- 95.8.4 Optical Modulation Amplitude (OMA)
- 95.8.5 Transmitter and dispersion eye closure (TDEC) [Go to Page]
- 95.8.5.1 TDEC conformance test setup
- 95.8.5.2 TDEC measurement method
- 95.8.6 Extinction ratio
- 95.8.7 Transmitter optical waveform (transmit eye)
- 95.8.8 Stressed receiver sensitivity [Go to Page]
- 95.8.8.1 Stressed receiver conformance test block diagram
- 95.8.8.2 Stressed receiver conformance test signal characteristics and calibration
- 95.8.8.3 J2 and J4 Jitter
- 95.8.8.4 Stressed receiver conformance test signal verification
- 95.8.8.5 Sinusoidal jitter for receiver conformance test
- 95.9 Safety, installation, environment, and labeling [Go to Page]
- 95.9.1 General safety
- 95.9.2 Laser safety
- 95.9.3 Installation
- 95.9.4 Environment
- 95.9.5 Electromagnetic emission
- 95.9.6 Temperature, humidity, and handling
- 95.9.7 PMD labeling requirements
- 95.10 Fiber optic cabling model
- 95.11 Characteristics of the fiber optic cabling (channel) [Go to Page]
- 95.11.1 Optical fiber cable
- 95.11.2 Optical fiber connection [Go to Page]
- 95.11.2.1 Connection insertion loss
- 95.11.2.2 Maximum discrete reflectance
- 95.11.3 Medium Dependent Interface (MDI) [Go to Page]
- 95.11.3.1 Optical lane assignments
- 95.11.3.2 Medium Dependent Interface (MDI) requirements
- 95.12 Protocol implementation conformance statement (PICS) proforma for Clause 95, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-SR4 [Go to Page]
- 95.12.1 Introduction
- 95.12.2 Identification [Go to Page]
- 95.12.2.1 Implementation identification
- 95.12.2.2 Protocol summary
- 95.12.3 Major capabilities/options
- 95.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-SR4 [Go to Page]
- 95.12.4.1 PMD functional specifications
- 95.12.4.2 Management functions
- 95.12.4.3 PMD to MDI optical specifications for 100GBASE-SR4
- 95.12.4.4 Optical measurement methods
- 95.12.4.5 Environmental specifications
- 95.12.4.6 Characteristics of the fiber optic cabling and MDI
- Annex A (informative) Bibliography
- Annex 83A (normative) 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s ten-lane Attachment Unit Interface (CAUI-10) [Go to Page]
- 83A.1 Overview [Go to Page]
- 83A.1.1 Summary of major concepts
- 83A.1.2 Rate of operation
- 83A.2 XLAUI/CAUI-10 link block diagram
- 83A.3 XLAUI/CAUI-10 electrical characteristics [Go to Page]
- 83A.3.1 Signal levels
- 83A.3.2 Signal paths
- 83A.3.2a EEE operation
- 83A.3.3 Transmitter characteristics [Go to Page]
- 83A.3.3.1 Output amplitude [Go to Page]
- 83A.3.3.1.1 Amplitude and swing
- 83A.3.3.6 Global transmit disable function
- 83A.3.4 Receiver characteristics [Go to Page]
- 83A.3.4.2 Input signal definition
- 83A.3.4.5 AC coupling
- 83A.3.4.6 Jitter tolerance
- 83A.3.4.7 Global energy detect function
- 83A.4 Interconnect characteristics
- 83A.5 Electrical parameter measurement methods [Go to Page]
- 83A.5.1 Transmit jitter
- 83A.5.2 Receiver tolerance
- 83A.6 Environmental specifications [Go to Page]
- 83A.6.4 Electromagnetic compatibility
- 83A.6.5 Temperature and humidity
- 83A.7 Protocol implementation conformance statement (PICS) proforma for Annex 83A, 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s ten-lane Attachment Unit Interface (CAUI-10) [Go to Page]
- 83A.7.1 Introduction
- 83A.7.2 Identification [Go to Page]
- 83A.7.2.2 Protocol summary
- 83A.7.3 Major capabilities/options
- 83A.7.4 XLAUI/CAUI-10 transmitter requirements
- 83A.7.5 XLAUI/CAUI-10 receiver requirements
- 83A.7.6 Electrical measurement methods
- Annex 83B (normative) Chip-to-module 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s ten-lane Attachment Unit Interface (CAUI-10) [Go to Page]
- 83B.1 Overview
- 83B.2 Compliance point specifications for chip-to-module XLAUI/CAUI-10 [Go to Page]
- 83B.2.1 Module specifications
- 83B.2.2 Host specifications
- 83B.2.3 Host input signal tolerance
- 83B.3 Environmental specifications [Go to Page]
- 83B.3.4 Electromagnetic compatibility
- 83B.3.5 Temperature and humidity
- 83B.4 Protocol implementation conformance statement (PICS) proforma for Annex 83B, Chip-to-module 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s ten-lane Attachment Unit Interface (CAUI-10) [Go to Page]
- 83B.4.1 Introduction
- 83B.4.2 Identification [Go to Page]
- 83B.4.2.2 Protocol summary
- 83B.4.3 Major capabilities/options
- 83B.4.4 Module requirements
- 83B.4.5 Host requirements
- Annex 83C (informative) PMA sublayer partitioning examples [Go to Page]
- 83C.1 Partitioning examples with FEC [Go to Page]
- 83C.1.2 FEC implemented with PMD
- 83C.1a Partitioning examples with RS-FEC [Go to Page]
- 83C.1a.2 Single CAUI-10 with RS-FEC
- 83C.2 Partitioning examples without FEC [Go to Page]
- 83C.2.2 Single XLAUI/CAUI-4 without FEC
- 83C.2.3 Separate SERDES for optical module interface
- Annex 83D (normative) Chip-to-chip 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83D.1 Overview
- 83D.2 CAUI-4 chip-to-chip compliance point definition
- 83D.3 CAUI-4 chip-to-chip electrical characteristics [Go to Page]
- 83D.3.1 CAUI-4 transmitter characteristics [Go to Page]
- 83D.3.1.1 Transmitter equalization settings
- 83D.3.2 Optional EEE operation
- 83D.3.3 CAUI-4 receiver characteristics [Go to Page]
- 83D.3.3.1 Receiver interference tolerance
- 83D.3.3.2 Transmitter equalization feedback (optional)
- 83D.3.4 Global energy detect function for optional EEE operation
- 83D.4 CAUI-4 chip-to-chip channel characteristics
- 83D.5 Example usage of the optional transmitter equalization feedback [Go to Page]
- 83D.5.1 Overview
- 83D.5.2 Tuning equalization settings on lane 0 in the transmit direction
- 83D.5.3 Tuning equalization settings on lane 0 in the receive direction
- 83D.6 Protocol implementation conformance statement (PICS) proforma for Annex 83D, Chip-to-chip 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83D.6.1 Introduction
- 83D.6.2 Identification [Go to Page]
- 83D.6.2.1 Implementation identification
- 83D.6.2.2 Protocol summary
- 83D.6.3 Major capabilities/options
- 83D.6.4 PICS proforma tables for chip-to-chip 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83D.6.4.1 Transmitter
- 83D.6.4.2 Receiver
- 83D.6.4.3 Channel
- Annex 83E (normative) Chip-to-module 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83E.1 Overview [Go to Page]
- 83E.1.1 Bit error ratio
- 83E.2 CAUI-4 chip-to-module compliance point definitions
- 83E.3 CAUI-4 chip-to-module electrical characteristics [Go to Page]
- 83E.3.1 CAUI-4 host output characteristics [Go to Page]
- 83E.3.1.1 Signaling rate and range
- 83E.3.1.2 Signal levels
- 83E.3.1.3 Output return loss
- 83E.3.1.4 Differential termination mismatch
- 83E.3.1.5 Transition time
- 83E.3.1.6 Host output eye width and eye height [Go to Page]
- 83E.3.1.6.1 Reference receiver for host output eye width and eye height evaluation
- 83E.3.2 CAUI-4 module output characteristics [Go to Page]
- 83E.3.2.1 Module output eye width and eye height [Go to Page]
- 83E.3.2.1.1 Reference receiver for module output eye width and eye height evaluation
- 83E.3.3 CAUI-4 host input characteristics [Go to Page]
- 83E.3.3.1 Input return loss
- 83E.3.3.2 Host stressed input test [Go to Page]
- 83E.3.3.2.1 Host stressed input test procedure
- 83E.3.4 CAUI-4 module input characteristics [Go to Page]
- 83E.3.4.1 Module stressed input test [Go to Page]
- 83E.3.4.1.1 Module stressed input test procedure
- 83E.4 CAUI-4 measurement methodology [Go to Page]
- 83E.4.1 HCB/MCB characteristics
- 83E.4.2 Eye width and eye height measurement method [Go to Page]
- 83E.4.2.1 Vertical eye closure
- 83E.5 Protocol implementation conformance statement (PICS) proforma for Annex 83E, Chip-to-module 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83E.5.1 Introduction
- 83E.5.2 Identification [Go to Page]
- 83E.5.2.1 Implementation identification
- 83E.5.2.2 Protocol summary
- 83E.5.3 Major capabilities/options
- 83E.5.4 PICS proforma tables for chip-to-module 100 Gb/s four-lane Attachment Unit Interface (CAUI-4) [Go to Page]
- 83E.5.4.1 Host output
- 83E.5.4.2 Module output
- 83E.5.4.3 Host input
- 83E.5.4.4 Module input
- Annex 93A (normative) Specification methods for electrical channels [Go to Page]
- 93A.1 Channel Operating Margin
- Back cover [Go to Page]
