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IEEE Standard FASTBUS Modular High-Speed Data Acquisition and Control System and IEEE FASTBUS Standard Routines, 1993
- 960-1993.pdf [Go to Page]
- Title Page
- Introduction
- Participants
- CONTENTS
- 1. Introduction and general information [Go to Page]
- 1.1. Document online
- 1.2. System overview
- 2. Conventions, definitions, abbreviations, symbols and references [Go to Page]
- 2.1. Interpretation of this standard
- 2.2. Notations and logic signal conventions
- 2.3. Definitions
- 2.4. Abbreviations
- 2.5. Symbols
- 2.6. References
- 3. Signals, signal lines, and pins [Go to Page]
- 3.1. Types of signal lines
- 3.2. Signal nomenclature
- 3.3. Brief description of signals, lines, and pins
- 3.4. Bus loading
- 4. FASTBUS operations: Addressing [Go to Page]
- 4.1. Logical addressing
- 4.2. Geographical addressing
- 4.3. Broadcast addressing
- 4.4. Secondary addressing
- 4.5. Sparse data scan and pattern select operation
- 5. FASTBUS operations: Timing, sequences and responses [Go to Page]
- 5.1. General master/slave timing requirements
- 5.2. Primary address cycles
- 5.3. Operations
- 5.4. Use of reset bus (RB)
- 5.5. Device response to POWER ON
- 5.6. State diagrams for FASTBUS operations
- 6. Bus arbitration [Go to Page]
- 6.1. Bus line usage for the arbitration process
- 6.2. The arbitration process
- 6.3. Arbitration rules
- 6.4. Systemwide arbitration
- 7. Ancillary logic on a segment [Go to Page]
- 7.1. Arbitration timing control (ATC)
- 7.2. Geographical address control
- 7.3. System handshake generation (broadcast)
- 7.4. Run/Halt control and bus halted
- 7.5. Terminators
- 7.6. Ancillary logic for crate segments
- 7.7. Ancillary logic for cable segments
- 8. Control and status register space [Go to Page]
- 8.1. Selective set and clear functions
- 8.2. Normal CSR space allocation
- 8.3. CSR register 0
- 8.4. CSR register 1
- 8.5. CSR register 2
- 8.6. CSR register 3
- 8.7. CSR register 4
- 8.8. CSR register 5
- 8.9. CSR register 6
- 8.10. CSR register 7
- 8.11. CSR register 8
- 8.12. CSR register 9 and CSR registers 1Ch to 1Fh
- 8.13. CSR registers Ah to Fh
- 8.14. CSR registers 20h to 3Fh
- 8.15. CSR registers 70h to 81h
- 8.16. CSR registers A0h to AFh, B0h and C0h to CFh
- 8.17. CSR registers 8000 0000h to BFFF FFFFh, parameter space
- 8.18. Clearing of CSR bits
- 8.19. CSR Register 18
- 8.20. CSR register 19
- 9. Interrupts [Go to Page]
- 9.1. Interrupt operation
- 9.2. The service request line
- 9.3. SR line saturation
- 10. Interconnection of Segment [Go to Page]
- 10.1. Types of segment interconnects
- 10.2. Operation passing
- 10.3. Contention resolution
- 10.4. Route tables
- 10.5. Control and status registers
- 10.6. Route tables
- 10.7. SI actions
- 10.8. Base address register
- 11. Block and pipelined transfers [Go to Page]
- 11.1. Block and pipelined transfer termination
- 11.2. Block transfer internal address incrementation
- 11.3. FIFOs and data transfer errors
- 11.4. Multi-module data transfers
- 12. Signal characteristics [Go to Page]
- 12.1. Signal levels
- 13. Modules [Go to Page]
- 13.1. Module circuit board
- 13.2. Connectors
- 13.3. Temperature considerations and power dissipation
- 13.4. Front Panel
- 13.5. Module activity indicators
- 13.6. Labeling of power requirements
- 13.7. Transients
- 14. Crates [Go to Page]
- 14.1. Crate construction
- 14.2. Crate backplane
- 14.3. Cooling
- 14.4. Run/Halt switch assembly
- 14.5. Circuit boards mounted at rear of backplane
- 14.6. Crate markings
- 14.7. Contacts for static charge discharge
- 15. Power
- 16. Cable segment [Go to Page]
- 16.1. Signals on a a cable segment
- 16.2. Cable segment connectors and contact assignments
- Annex A Requirements for various implementations
- Annex B Front panel interconnections for ECL
- Annex C Cable segment implementation
- Annex D Implementation examples of master requirements
- Annex E FASTBUS segment interconnect type S-1
- Annex F Module implementation
- Annex G Examples of type A crate implementation
- Annex H Examples of Type W crate and Type W module assembly
- Annex I Typical power supplies
- Annex J Non-zero status handling procedures
- Annex K Components
- Annex L Construction and system requirements
- Annex M System and circuit protection
- Annex N Multi-module data transfer specification (MDT-1)
- 1177-1993.pdf [Go to Page]
- Title Page
- Introduction
- Participants
- Abbreviated Table of Contents
- CONTENTS
- 1. Overview [Go to Page]
- 1.1 Scope and object
- 1.2 Interpretation of this Standard
- 1.3 Document Overview.
- 1.4 References
- 2. Basic concepts [Go to Page]
- 2.1 Terminology
- 2.2 Environment
- 2.3 Naming conventions
- 2.4 Parameters to routines: Type and direction
- 2.5 Buffer Parameters.
- 2.6 Categories of routines
- 3. Environment management and delayed action [Go to Page]
- 3.1 Open and close FASTBUS session
- 3.2 Environment management routines
- 3.3 Delayed execution and list validation
- 4. Operational parameters [Go to Page]
- 4.1 Introduction
- 4.2 Definition of operational parameter
- 4.3 Operational parameter routines
- 4.4 Overall and error handling operational parameters
- 4.5 FASTBUS protocol, timeout and retry operational parameters
- 5. Data Buffers [Go to Page]
- 5.1 Buffer access arguments
- 5.2 Sequential data buffer routines
- 6. Simple transaction routines [Go to Page]
- 6.1 Conditions governing transaction and compound routines
- 6.2 Simple FASTBUS transaction routines
- 7. Compound transaction routines [Go to Page]
- 7.1 Access segment interconnect route table
- 7.2 Move data between FASTBUS devices
- 7.3 Read-modify-write a FASTBUS location
- 7.4 Data gathering routines
- 7.5 Send a FASTBUS Interrupt Message.
- 8. Primitive FASTBUS action routines [Go to Page]
- 8.1 Introduction
- 8.2 Parameters
- 8.3 Single cycle routines
- 8.4 FASTBUS line access
- 9. FASTBUS SR and interrupt message routines [Go to Page]
- 9.1 Introduction
- 9.2 FASTBUS service request
- 9.3 FASTBUS interrupt message routines
- 10. Synchronization, system resource and port routines [Go to Page]
- 10.1 Synchronization tools
- 10.2 Reset FASTBUS port
- 10.3 FASTBUS port allocation
- 10.4 Get version numbers
- 10.5 Report a port FASTBUS error
- 10.6 Generate a port error message
- 11. Status and error handling [Go to Page]
- 11.1 Introduction
- 11.2 Error and return codes
- 11.3 Summary and supplementary status
- 11.4 Restricting generation of status information
- 11.5 Delayed mode execution status
- 11.6 Severity
- 11.7 Set the severity of an error code
- 11.8 Response to errors in execution
- 11.9 Automatic error reporting
- 11.10 Access to summary status information
- 11.11 Access to supplementary status information
- 11.12 Routines for the Manipulation of Error Codes.
- 11.13 Report a FASTBUS error
- 11.14 Generate an error message
- 12. Error codes [Go to Page]
- 12.1 Standard set of error codes
- Annex A. Summary of routine names and parameters
- Annex B. List of reserved names
- Annex C. FORTRAN 77 data types [Go to Page]
